LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.mips_types.all;

ENTITY e_mips_regs IS
    PORT (
        rst:         IN  std_logic;
        clk:         IN  std_logic;
        i_rd_a_no:   IN  std_logic_vector( 4 DOWNTO 0);
        o_rd_a_data: OUT std_logic_vector(31 DOWNTO 0);
        i_rd_b_no:   IN  std_logic_vector( 4 DOWNTO 0);
        o_rd_b_data: OUT std_logic_vector(31 DOWNTO 0);
        i_wr_no:     IN  std_logic_vector( 4 DOWNTO 0);
        i_wr_data:   IN  std_logic_vector(31 DOWNTO 0);
        i_wr_en:     IN  std_logic
    );
END ENTITY e_mips_regs;

ARCHITECTURE a_mips_regs OF e_mips_regs IS

    SUBTYPE t_idx IS natural RANGE 31 DOWNTO 0;

    TYPE t_regs IS ARRAY(t_idx) OF std_logic_vector(31 DOWNTO 0);

    SIGNAL r_regs: t_regs;

    FUNCTION no2idx(no: std_logic_vector(4 DOWNTO 0)) RETURN natural IS
    BEGIN
        RETURN to_integer(unsigned(no));
    END FUNCTION no2idx;

BEGIN

    o_rd_a_data <= r_regs(no2idx(i_rd_a_no));

    o_rd_b_data <= r_regs(no2idx(i_rd_b_no));

    p_write: PROCESS(rst, clk)
    BEGIN
        IF rst = '1' THEN
            r_regs <= (OTHERS => X"00000000");
        ELSIF rising_edge(clk) THEN
            IF i_wr_en = '1' AND i_wr_no /= "00000" THEN
                r_regs(no2idx(i_wr_no)) <= i_wr_data;
            END IF;
        END IF;
    END PROCESS p_write;

END ARCHITECTURE a_mips_regs;