LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY e_io_cyc_cnt IS
    PORT (
        rst:       IN  std_logic;
        clk:       IN  std_logic;
        o_rd_data: OUT std_logic_vector(31 DOWNTO 0);
        i_wr_data: IN  std_logic_vector(31 DOWNTO 0);
        i_wr_en:   IN  std_logic
    );
END ENTITY e_io_cyc_cnt;

ARCHITECTURE a_io_cyc_cnt OF e_io_cyc_cnt IS

    SIGNAL n_cnt: std_logic_vector(31 DOWNTO 0);
    SIGNAL r_cnt: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');

BEGIN

    o_rd_data <= r_cnt;

    p_write: PROCESS(r_cnt, i_wr_data, i_wr_en)
    BEGIN
        IF i_wr_en = '1' THEN
            n_cnt <= i_wr_data;
        ELSE
            n_cnt <= std_logic_vector(unsigned(r_cnt) + to_unsigned(1, 32));
        END IF;
    END PROCESS p_write;

    p_sync: PROCESS(rst, clk)
    BEGIN
        IF rst = '1' THEN
            r_cnt <= (OTHERS => '0');
        ELSIF rising_edge(clk) THEN
            r_cnt <= n_cnt;
        END IF;
    END PROCESS p_sync;

END ARCHITECTURE a_io_cyc_cnt;