LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.io_lcd_pins.all;

ENTITY e_system IS
    PORT (
        rst:        IN  std_logic;
        clk:        IN  std_logic;
        pin_o_leds: OUT std_logic_vector(7 DOWNTO 0);
        pin_o_lcd:  OUT t_io_lcd_pins
    );
END ENTITY e_system;

ARCHITECTURE a_system OF e_system IS

    SIGNAL s_instr_addr:   std_logic_vector(31 DOWNTO 0);
    SIGNAL s_instr_data:   std_logic_vector(31 DOWNTO 0);
    SIGNAL s_dbus_addr:    std_logic_vector(31 DOWNTO 0);
    SIGNAL s_dbus_rd_data: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_dbus_wr_data: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_dbus_wr_en:   std_logic_vector( 3 DOWNTO 0);
    SIGNAL s_data_addr:    std_logic_vector(31 DOWNTO 0);
    SIGNAL s_data_rd_data: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_data_wr_data: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_data_wr_en:   std_logic_vector( 3 DOWNTO 0);
    SIGNAL s_leds_rd_data: std_logic_vector( 7 DOWNTO 0);
    SIGNAL s_leds_wr_data: std_logic_vector( 7 DOWNTO 0);
    SIGNAL s_leds_wr_en:   std_logic;
    SIGNAL s_lcd_rd_data: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_lcd_wr_data: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_lcd_wr_en:   std_logic_vector( 3 DOWNTO 0);
    SIGNAL s_cyc_cnt_rd_data: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_cyc_cnt_wr_data: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_cyc_cnt_wr_en:   std_logic;

    COMPONENT e_mips_core IS
        PORT (
            rst:            IN  std_logic;
            clk:            IN  std_logic;
            i_stall:        IN  std_logic;
            o_instr_addr:   OUT std_logic_vector(31 DOWNTO 0);
            i_instr_data:   IN  std_logic_vector(31 DOWNTO 0);
            o_data_addr:    OUT std_logic_vector(31 DOWNTO 0);
            i_data_rd_data: IN  std_logic_vector(31 DOWNTO 0);
            o_data_wr_data: OUT std_logic_vector(31 DOWNTO 0);
            o_data_wr_en:   OUT std_logic_vector( 3 DOWNTO 0)
        );
    END COMPONENT e_mips_core;

    COMPONENT e_rom IS
        GENERIC (
            addr_width: INTEGER
        );
        PORT (
            clk:    IN  std_logic;
            i_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
            o_data: OUT std_logic_vector(            31 DOWNTO 0)
        );
    END COMPONENT e_rom;

    COMPONENT e_ram IS
        GENERIC (
            addr_width: natural;
            data_width: natural
        );
        PORT (
            clk:       IN  std_logic;
            i_addr:    IN  std_logic_vector(addr_width - 1 DOWNTO 0);
            o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
            i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
            i_wr_en:   IN  std_logic
        );
    END COMPONENT e_ram;

    COMPONENT e_io_leds IS
        PORT (
            rst:        IN  std_logic;
            clk:        IN  std_logic;
            o_rd_data:  OUT std_logic_vector(7 DOWNTO 0);
            i_wr_data:  IN  std_logic_vector(7 DOWNTO 0);
            i_wr_en:    IN  std_logic;
            pin_o_leds: OUT std_logic_vector(7 DOWNTO 0)
        );
    END COMPONENT e_io_leds;

    COMPONENT e_io_lcd IS
        PORT (
            rst:       IN  std_logic;
            clk:       IN  std_logic;
            o_rd_data: OUT std_logic_vector(31 DOWNTO 0);
            i_wr_data: IN  std_logic_vector(31 DOWNTO 0);
            i_wr_en:   IN  std_logic_vector( 3 DOWNTO 0);
            pin_o_lcd: OUT t_io_lcd_pins
        );
    END COMPONENT e_io_lcd;

    COMPONENT e_io_cyc_cnt IS
        PORT (
            rst:       IN  std_logic;
            clk:       IN  std_logic;
            o_rd_data: OUT std_logic_vector(31 DOWNTO 0);
            i_wr_data: IN  std_logic_vector(31 DOWNTO 0);
            i_wr_en:   IN  std_logic
        );
    END COMPONENT e_io_cyc_cnt;

BEGIN

    core: e_mips_core
        PORT MAP (
            rst            => rst,
            clk            => clk,
            i_stall        => '0',
            o_instr_addr   => s_instr_addr,
            i_instr_data   => s_instr_data,
            o_data_addr    => s_dbus_addr,
            i_data_rd_data => s_dbus_rd_data,
            o_data_wr_data => s_dbus_wr_data,
            o_data_wr_en   => s_dbus_wr_en
        );

    instr: e_rom
        GENERIC MAP (
            addr_width => 10
        )
        PORT MAP (
            clk    => clk,
            i_addr => s_instr_addr(11 DOWNTO 2),
            o_data => s_instr_data
        );

    p_dbus: PROCESS(s_dbus_addr, s_dbus_wr_data, s_dbus_wr_en,
                    s_data_rd_data,
                    s_leds_rd_data,
                    s_lcd_rd_data,
                    s_cyc_cnt_rd_data)
        VARIABLE v_wr_en_word: std_logic;
    BEGIN
        v_wr_en_word := s_dbus_wr_en(0) AND s_dbus_wr_en(1) AND
                        s_dbus_wr_en(2) AND s_dbus_wr_en(3);
        s_dbus_rd_data <= (OTHERS => '0');
        s_data_addr    <= (OTHERS => '0');
        s_data_wr_data <= (OTHERS => '0');
        s_data_wr_en   <= (OTHERS => '0');
        s_leds_wr_data <= (OTHERS => '0');
        s_leds_wr_en   <= '0';
        s_lcd_wr_data <= (OTHERS => '0');
        s_lcd_wr_en   <= (OTHERS => '0');
        s_cyc_cnt_wr_data <= (OTHERS => '0');
        s_cyc_cnt_wr_en   <= '0';
        IF s_dbus_addr(31) = '0' THEN
            s_dbus_rd_data <= s_data_rd_data;
            s_data_addr    <= s_dbus_addr;
            s_data_wr_data <= s_dbus_wr_data;
            s_data_wr_en   <= s_dbus_wr_en;
        ELSIF s_dbus_addr(31 DOWNTO 16) = X"8000" THEN
            CASE s_dbus_addr(15 DOWNTO 8) IS
                WHEN X"00" =>
                    s_dbus_rd_data <= X"000000" & s_leds_rd_data;
                    s_leds_wr_data <= s_dbus_wr_data(7 DOWNTO 0);
                    s_leds_wr_en   <= s_dbus_wr_en(0);
                WHEN X"01" =>
                    s_dbus_rd_data <= s_lcd_rd_data;
                    s_lcd_wr_data  <= s_dbus_wr_data;
                    s_lcd_wr_en    <= s_dbus_wr_en;
                WHEN X"10" =>
                    s_dbus_rd_data    <= s_cyc_cnt_rd_data;
                    s_cyc_cnt_wr_data <= s_dbus_wr_data;
                    s_cyc_cnt_wr_en   <= v_wr_en_word;
                WHEN OTHERS => NULL;
            END CASE;
        END IF;
    END PROCESS p_dbus;

    data: FOR i IN 0 TO 3 GENERATE
        databank: e_ram
            GENERIC MAP (
                addr_width => 10,
                data_width => 8
            )
            PORT MAP (
                clk       => clk,
                i_addr    => s_data_addr(11 DOWNTO 2),
                o_rd_data => s_data_rd_data(i*8+7 DOWNTO i*8),
                i_wr_data => s_data_wr_data(i*8+7 DOWNTO i*8),
                i_wr_en   => s_data_wr_en(i)
            );
    END GENERATE data;

    leds: e_io_leds
        PORT MAP (
            rst        => rst,
            clk        => clk,
            o_rd_data  => s_leds_rd_data,
            i_wr_data  => s_leds_wr_data,
            i_wr_en    => s_leds_wr_en,
            pin_o_leds => pin_o_leds
        );

    lcd: e_io_lcd
        PORT MAP (
            rst       => rst,
            clk       => clk,
            o_rd_data => s_lcd_rd_data,
            i_wr_data => s_lcd_wr_data,
            i_wr_en   => s_lcd_wr_en,
            pin_o_lcd => pin_o_lcd
        );

    cyc_cnt: e_io_cyc_cnt
        PORT MAP (
            rst       => rst,
            clk       => clk,
            o_rd_data => s_cyc_cnt_rd_data,
            i_wr_data => s_cyc_cnt_wr_data,
            i_wr_en   => s_cyc_cnt_wr_en
        );

END ARCHITECTURE a_system;