LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE std.textio.all;
USE work.io_lcd_pins.all;
USE work.io_switches_pins.all;

ENTITY e_testbed IS
END ENTITY e_testbed;

ARCHITECTURE a_testbed OF e_testbed IS

    COMPONENT e_system IS
        PORT (
            clk:            IN  std_logic;
            pin_o_leds:     OUT std_logic_vector(7 DOWNTO 0);
            pin_o_lcd:      OUT t_io_lcd_pins;
            pin_i_switches: IN  t_io_switches_pins;
            pin_i_uart_rx:  IN  std_logic;
            pin_o_uart_tx:  OUT std_logic
        );
    END COMPONENT e_system;

    SIGNAL s_clk:             std_logic;
    SIGNAL pin_leds:          std_logic_vector(7 DOWNTO 0);
    SIGNAL pin_lcd:           t_io_lcd_pins;
    SIGNAL pin_uart_loopback: std_logic;

BEGIN

    system: e_system
        PORT MAP (
            clk            => s_clk,
            pin_o_leds     => pin_leds,
            pin_o_lcd      => pin_lcd,
            pin_i_switches => (sw => (OTHERS => '0'), OTHERS => '0'),
            pin_i_uart_rx  => pin_uart_loopback,
            pin_o_uart_tx  => pin_uart_loopback
        );

    p_rst_clk: PROCESS
    BEGIN
        s_clk        <= '0';
        WHILE TRUE LOOP
            WAIT FOR 10 ns;
            s_clk <= '1';
            WAIT FOR 10 ns;
            s_clk <= '0';
        END LOOP;
    END PROCESS p_rst_clk;

END ARCHITECTURE a_testbed;