s_clk s_clk pin_leds[7:0] pin_leds[7:0] pin_lcd pin_lcd pin_i_uart_rx pin_i_uart_rx pin_o_uart_tx pin_o_uart_tx [29] r_regs[29] HEXRADIX o_instr_addr[31:0] o_instr_addr[31:0] HEXRADIX i_instr_data[31:0] i_instr_data[31:0] HEXRADIX s_stall s_stall s_core_req s_core_req s_core_grant s_core_grant s_core_addr[31:0] s_core_addr[31:0] s_core_rd_data[31:0] s_core_rd_data[31:0] s_core_rd_en[3:0] s_core_rd_en[3:0] s_core_wr_data[31:0] s_core_wr_data[31:0] s_core_wr_en[3:0] s_core_wr_en[3:0] s_ethbm_req s_ethbm_req s_ethbm_grant s_ethbm_grant s_ethbm_addr[31:0] s_ethbm_addr[31:0] s_ethbm_rd_data[31:0] s_ethbm_rd_data[31:0] s_ethbm_rd_en[3:0] s_ethbm_rd_en[3:0] s_ethbm_wr_data[31:0] s_ethbm_wr_data[31:0] s_ethbm_wr_en[3:0] s_ethbm_wr_en[3:0] s_dbus_addr[31:0] s_dbus_addr[31:0] s_dbus_rd_data[31:0] s_dbus_rd_data[31:0] s_dbus_rd_en[3:0] s_dbus_rd_en[3:0] s_dbus_wr_data[31:0] s_dbus_wr_data[31:0] s_dbus_wr_en[3:0] s_dbus_wr_en[3:0]