LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE work.mips_types.all; ENTITY e_mips_shifter IS PORT ( i_arith: IN std_logic; i_left: IN std_logic; i_val: IN std_logic_vector(31 DOWNTO 0); i_num: IN std_logic_vector(31 DOWNTO 0); o_val: OUT std_logic_vector(31 DOWNTO 0) ); END ENTITY e_mips_shifter; ARCHITECTURE a_mips_shifter OF e_mips_shifter IS SIGNAL s_fill: std_logic; FUNCTION l_shift(b: std_logic; val: std_logic_vector(31 DOWNTO 0); n: natural) RETURN std_logic_vector IS VARIABLE v_fill: std_logic_vector(31 DOWNTO 0); BEGIN v_fill := (OTHERS => '0'); IF b = '1' THEN RETURN val(31 - n DOWNTO 0) & v_fill(n - 1 DOWNTO 0); ELSE RETURN val; END IF; END FUNCTION l_shift; FUNCTION r_shift(b: std_logic; val: std_logic_vector(31 DOWNTO 0); fill: std_logic; n: natural) RETURN std_logic_vector IS VARIABLE v_fill: std_logic_vector(31 DOWNTO 0); BEGIN v_fill := (OTHERS => fill); IF b = '1' THEN RETURN v_fill(n - 1 DOWNTO 0) & val(31 DOWNTO n); ELSE RETURN val; END IF; END FUNCTION r_shift; BEGIN s_fill <= i_arith AND i_val(31); p_shift: PROCESS(i_left, i_val, i_num, s_fill) VARIABLE v1: std_logic_vector(31 DOWNTO 0); VARIABLE v2: std_logic_vector(31 DOWNTO 0); VARIABLE v3: std_logic_vector(31 DOWNTO 0); VARIABLE v4: std_logic_vector(31 DOWNTO 0); VARIABLE v5: std_logic_vector(31 DOWNTO 0); CONSTANT zero: std_logic_vector(31 DOWNTO 5) := (OTHERS => '0'); BEGIN IF i_left = '1' THEN v1 := l_shift(i_num(0), i_val, 1); v2 := l_shift(i_num(1), v1, 2); v3 := l_shift(i_num(2), v2, 4); v4 := l_shift(i_num(3), v3, 8); v5 := l_shift(i_num(4), v4, 16); ELSE v1 := r_shift(i_num(0), i_val, s_fill, 1); v2 := r_shift(i_num(1), v1, s_fill, 2); v3 := r_shift(i_num(2), v2, s_fill, 4); v4 := r_shift(i_num(3), v3, s_fill, 8); v5 := r_shift(i_num(4), v4, s_fill, 16); END IF; IF i_num(31 DOWNTO 5) = zero THEN o_val <= v5; ELSE o_val <= (OTHERS => s_fill); END IF; END PROCESS p_shift; END ARCHITECTURE a_mips_shifter;