mips_sys

implented basic system with core, instr memory, data memory

Stefan Schuermans authored on 2012-02-06 21:28:00

second version of multiplier (slower, i.e. more stages -> faster clock)

Stefan Schuermans authored on 2012-02-05 21:39:45

implemented ... and link -> MIPSel1 core complete

Stefan Schuermans authored on 2012-02-05 21:16:11

implemented divider

Stefan Schuermans authored on 2012-02-05 20:59:58

moved multiplier to own module

Stefan Schuermans authored on 2012-02-05 19:14:55

implemented multiplier

Stefan Schuermans authored on 2012-02-05 18:33:53

decoding MULT(U)/DIV(U) -> MIPSel1 decoder complete

Stefan Schuermans authored on 2012-02-05 17:32:53

implemented M T/F HI/LO

Stefan Schuermans authored on 2012-02-05 17:23:27

implementation of LWL, LWR

Stefan Schuermans authored on 2012-02-05 16:25:55

decoding of LWL, LWR, SWL, SWR

Stefan Schuermans authored on 2012-02-05 16:25:41

implemented simple load instructions

Stefan Schuermans authored on 2012-02-05 16:02:11

whitespace changes

Stefan Schuermans authored on 2012-02-05 13:59:54

implemented simple store instructions, preparations for load instructions

Stefan Schuermans authored on 2012-02-05 13:58:17

fix sensitivity lists

Stefan Schuermans authored on 2012-02-05 13:21:46

fix unused signals

Stefan Schuermans authored on 2012-02-05 13:21:27

implemented "register 0 is always 0" in a faster way

Stefan Schuermans authored on 2012-01-26 21:17:30

added decoding of simple load/store instructions and lui instruction implemented lui instruction fix syntax bug in regs

Stefan Schuermans authored on 2012-01-26 20:50:15

fix sensitivity list

Stefan Schuermans authored on 2012-01-26 20:42:52

register 0 is always 0

Stefan Schuermans authored on 2012-01-26 20:42:09

implement jump logic, implement instruction fetch

Stefan Schuermans authored on 2012-01-25 23:17:28