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Tree: 12f75e02a37862df28cbbbffa9f8abd82819e9f2
    master
March 1, 2012
  • Stefan Schuermans
    implemented multi-master feature for data bus extended ethernet block to have busmaster signals (dummy functionality up to now)

    Stefan Schuermans authored on 2012-03-01 21:24:14

    12f75e0
  • Stefan Schuermans
    converted core to use req and grant signals to access data bus

    Stefan Schuermans authored on 2012-03-01 21:23:47

    77114e6
  • Stefan Schuermans
    keep read enable active during read

    Stefan Schuermans authored on 2012-03-01 20:04:09

    1d0a24c
February 29, 2012
  • Stefan Schuermans
    changed MIPS core to use read and write ack instead of stall input

    Stefan Schuermans authored on 2012-02-29 21:28:37

    4059dff
  • Stefan Schuermans
    shortcut to switch between HW and simulation config

    Stefan Schuermans authored on 2012-02-29 21:28:34

    c559f2f
February 26, 2012
  • Stefan Schuermans
    add read_enable signal to data bus and some peripherals

    Stefan Schuermans authored on 2012-02-26 21:20:53

    22b4569
  • Stefan Schuermans
    fix reading (1 cycle latency) from ethernet peripheral

    Stefan Schuermans authored on 2012-02-26 18:26:02

    3189179
February 21, 2012
  • Stefan Schuermans
    timing for ethernet clocks

    Stefan Schuermans authored on 2012-02-21 21:39:56

    e898509
  • Stefan Schuermans
    removed bottleneck from data bus implementation, now meets timing even with keep_hierarchy

    Stefan Schuermans authored on 2012-02-21 20:40:30

    65b2622
February 20, 2012
  • Stefan Schuermans
    begin of ethernet RX implementation, so far only test interface to core, does not meet timing

    Stefan Schuermans authored on 2012-02-20 21:16:03

    47f05ce
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