mips_sys

migration to Xilinx 13.4
Parent 00d70be
Stefan Schuermans

Stefan Schuermans commited on 2012-03-24 14:06:11
Showing 4 changed files, with 11 additions and 12 deletions.

.gitignore
View file @ 70d97c2
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@@ -14,6 +14,8 @@
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 *.map
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 *.mcs
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 *.mrp
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+*.msd
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+*.msk
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 *.ncd
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 *.ngc
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 *.ngd
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@@ -25,6 +27,8 @@
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 *.prj
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 *.prm
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 *.ptwx
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+*.rbb
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+*.rbd
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 *.stx
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 *.syr
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 *.tcl
Default.wcfg
View file @ 70d97c2
... ... 
@@ -3,7 +3,7 @@
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    <wave_state>
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    </wave_state>
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    <db_ref_list>
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-      <db_ref path="/home/stefan/spartan3/mips_sys/e_testbed_isim_beh.wdb" id="1" type="auto">
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+      <db_ref path="/home/stefan/spartan3/mips_sys/e_testbed_isim_beh1.wdb" id="1" type="auto">
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          <top_modules>
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             <top_module name="e_testbed" />
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             <top_module name="io_lcd_pins" />
... ... 
@@ -15,19 +15,14 @@
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          </top_modules>
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       </db_ref>
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    </db_ref_list>
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-   <WVObjectSize size="22" />
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+   <WVObjectSize size="21" />
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    <wvobject fp_name="/e_testbed/s_clk" type="logic" db_ref_id="1">
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       <obj_property name="ElementShortName">s_clk</obj_property>
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       <obj_property name="ObjectShortName">s_clk</obj_property>
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    </wvobject>
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-   <wvobject fp_name="/e_testbed/pin_leds" type="array" db_ref_id="1">
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-      <obj_property name="ElementShortName">pin_leds[7:0]</obj_property>
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-      <obj_property name="ObjectShortName">pin_leds[7:0]</obj_property>
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-      <obj_property name="Radix">HEXRADIX</obj_property>
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-   </wvobject>
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-   <wvobject fp_name="/e_testbed/pin_lcd" type="array" db_ref_id="1">
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-      <obj_property name="ElementShortName">pin_lcd</obj_property>
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-      <obj_property name="ObjectShortName">pin_lcd</obj_property>
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+   <wvobject fp_name="/e_testbed/s_leds" type="array" db_ref_id="1">
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+      <obj_property name="ElementShortName">s_leds[7:0]</obj_property>
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+      <obj_property name="ObjectShortName">s_leds[7:0]</obj_property>
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       <obj_property name="Radix">HEXRADIX</obj_property>
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    </wvobject>
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    <wvobject fp_name="/e_testbed/system/pin_i_uart_rx" type="logic" db_ref_id="1">
mips_sys.ipf
View file @ 70d97c2
mips_sys.xise
View file @ 70d97c2
... ... 
@@ -12,7 +12,7 @@
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     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
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   </header>
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-  <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
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+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
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   <files>
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     <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
... ... 
@@ -407,7 +407,7 @@
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     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
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     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
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     <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="40 ms" xil_pn:valueState="non-default"/>
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+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="50 ms" xil_pn:valueState="non-default"/>
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     <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
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     <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
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     <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
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