mips_sys

@@ -116,8 +116,6 @@ int eth_rx(void **pptr, unsigned int *psz)

  */

 void eth_tx(const void *ptr, unsigned int sz)

 {

-  while(sz & 3) /* pad with zeros */

-    ((unsigned char *)ptr)[sz++] = 0;

   eth_ptr[8] = (unsigned int)ptr; /* start */

   eth_ptr[9] = (unsigned int)ptr + sz; /* end */

   eth_ptr[10] = 1; /* set flag */

@@ -89,10 +89,9 @@ ARCHITECTURE a_io_eth OF e_io_eth IS

     SIGNAL n_rx_new_en:    std_logic;

     -- TX buffer registers

-    --   start: begin of buffer

-    --   end: address just behind buffer

+    --   start: begin of buffer (word-aligned)

+    --   end: address just behind buffer (NOT word-aligned)

     --   en: write 1 to start transmission, returns to zero if complete

-    --   all addresses are word-aligned

     SIGNAL r_tx_start: std_logic_vector(31 DOWNTO 0) := X"00000000";

     SIGNAL n_tx_start: std_logic_vector(31 DOWNTO 0);

     SIGNAL r_tx_end:   std_logic_vector(31 DOWNTO 0) := X"00000000";

@@ -105,8 +104,12 @@ ARCHITECTURE a_io_eth OF e_io_eth IS

     SIGNAL n_mac: std_logic_vector(47 DOWNTO 0);

     -- TX busmaster read state machine

+    --   pos: next address to read (NOT word-aligned)

+    --   rem: number of bytes remaining (NOT multiple of words size)

     SIGNAL r_tx_pos: std_logic_vector(31 DOWNTO 0) := X"00000000";

     SIGNAL n_tx_pos: std_logic_vector(31 DOWNTO 0);

+    SIGNAL r_tx_rem: signed          (31 DOWNTO 0) := X"00000000";

+    SIGNAL n_tx_rem: signed          (31 DOWNTO 0);

     -- busmaster write buffer

     SIGNAL s_wrbuf_wr_rdy:  std_logic;

@@ -528,13 +531,17 @@ BEGIN

         );

     -- TX busmaster read state machine

-    p_tx_rd_next: PROCESS(r_tx_pos, r_tx_start, s_txframe_en, s_txbuf_wr_en)

+    p_tx_rd_next: PROCESS(r_tx_pos, r_tx_rem, r_tx_start, r_tx_end,

+                          s_txframe_en, s_txbuf_wr_en)

     BEGIN

         n_tx_pos <= r_tx_pos;

+        n_tx_rem <= r_tx_rem;

         IF s_txframe_en = '1' THEN

             n_tx_pos <= r_tx_start;

+            n_tx_rem <= signed(r_tx_end) - signed(r_tx_start);

         ELSIF s_txbuf_wr_en = '1' THEN

             n_tx_pos <= std_logic_vector(unsigned(r_tx_pos) + X"00000004");

+            n_tx_rem <= r_tx_rem - X"00000004";

         END IF;

     END PROCESS p_tx_rd_next;

@@ -542,26 +549,38 @@ BEGIN

     BEGIN

         IF rst = '1' THEN

             r_tx_pos <= X"00000000";

+            r_tx_rem <= X"00000000";

         ELSIF rising_edge(clk) THEN

             r_tx_pos <= n_tx_pos;

+            r_tx_rem <= n_tx_rem;

         END IF;

     END PROCESS p_tx_rd_sync;

     -- busmaster read completed    

-    p_bm_rd: PROCESS(r_bm_rd, i_bm_rd_data)

+    p_bm_rd: PROCESS(r_bm_rd, r_tx_rem, i_bm_rd_data)

     BEGIN

         s_txbuf_wr_data <= X"00000000";

         s_txbuf_wr_en   <= '0';

         -- read was just completed

         IF r_bm_rd = '1' THEN

-            s_txbuf_wr_data <= i_bm_rd_data;

+            CASE r_tx_rem IS

+                WHEN X"00000000" => NULL;

+                WHEN X"00000001" => s_txbuf_wr_data( 7 DOWNTO 0)

+                                    <= i_bm_rd_data( 7 DOWNTO 0);

+                WHEN X"00000002" => s_txbuf_wr_data(15 DOWNTO 0)

+                                    <= i_bm_rd_data(15 DOWNTO 0);

+                WHEN X"00000003" => s_txbuf_wr_data(23 DOWNTO 0)

+                                    <= i_bm_rd_data(23 DOWNTO 0);

+                WHEN OTHERS      => s_txbuf_wr_data

+                                    <= i_bm_rd_data;

+            END CASE;

             s_txbuf_wr_en <= '1';

         END IF;

     END PROCESS p_bm_rd;

     -- bus master write (and request side of read)

     p_bm_wr: PROCESS(r_bm_rd,

-                     r_tx_en, r_tx_pos, r_tx_end, s_txbuf_wr_rdy,

+                     r_tx_en, r_tx_pos, r_tx_rem, s_txbuf_wr_rdy,

                      s_wrbuf_rd_rdy, s_wrbuf_rd_data, i_bm_grant)

         VARIABLE v_read:  boolean;

         VARIABLE v_write: boolean;

@@ -578,7 +597,7 @@ BEGIN

         --         space in buffer

         --   write: write request in write buffer

         v_read  := r_bm_rd = '0' AND r_tx_en = '1' AND

-                   r_tx_pos /= r_tx_end AND s_txbuf_wr_rdy = '1';

+                   r_tx_rem > X"00000000" AND s_txbuf_wr_rdy = '1';

         v_write := s_wrbuf_rd_rdy = '1';

         -- read access

         IF v_read THEN