LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY e_io_eth_txif IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
i_data: IN std_logic_vector(7 DOWNTO 0);
i_data_en: IN std_logic;
o_data_ack: OUT std_logic;
pin_i_tx_clk: IN std_logic;
pin_o_txd: OUT std_logic_vector(3 DOWNTO 0);
pin_o_tx_en: OUT std_logic
);
END ENTITY e_io_eth_txif;
ARCHITECTURE a_io_eth_txif OF e_io_eth_txif IS
TYPE t_out_state IS (out_idle, out_data_l, out_data_h);
SIGNAL r_out_state: t_out_state := out_idle;
SIGNAL n_out_state: t_out_state;
SIGNAL r_out_data: std_logic_vector(7 DOWNTO 0) := X"00";
SIGNAL n_out_data: std_logic_vector(7 DOWNTO 0);
SIGNAL s_fifo_wr_rdy: std_logic;
SIGNAL s_fifo_wr_data: std_logic_vector(7 DOWNTO 0);
SIGNAL s_fifo_wr_en: std_logic;
SIGNAL s_fifo_rd_rdy: std_logic;
SIGNAL s_fifo_rd_data: std_logic_vector(7 DOWNTO 0);
SIGNAL s_fifo_rd_en: std_logic;
COMPONENT e_block_fifo_dc IS
GENERIC (
addr_width: natural;
data_width: natural
);
PORT (
rst: IN std_logic;
wr_clk: IN std_logic;
o_wr_rdy: OUT std_logic;
i_wr_data: IN std_logic_vector(data_width - 1 DOWNTO 0);
i_wr_en: IN std_logic;
rd_clk: IN std_logic;
o_rd_rdy: OUT std_logic;
o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
i_rd_en: IN std_logic
);
END COMPONENT e_block_fifo_dc;
