LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.io_switches_pins.all;
ENTITY e_io_switches IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
i_addr: IN std_logic_vector( 0 DOWNTO 0);
o_rd_data: OUT std_logic_vector(31 DOWNTO 0);
pin_i_switches: IN t_io_switches_pins
);
END ENTITY e_io_switches;
ARCHITECTURE a_io_switches OF e_io_switches IS
SIGNAL n_sample: std_logic_vector(1 DOWNTO 0);
SIGNAL r_sample: std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL r_prev: std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL n_cnt: std_logic_vector(31 DOWNTO 0);
SIGNAL r_cnt: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
BEGIN
p_sample: PROCESS(pin_i_switches)
BEGIN
-- de-gray-code rotary inputs
IF pin_i_switches.rot_b = '1' THEN
IF pin_i_switches.rot_a = '1' THEN
n_sample <= "00";
ELSE
n_sample <= "11";
END IF;
ELSE
IF pin_i_switches.rot_a = '1' THEN
n_sample <= "01";
ELSE
n_sample <= "10";
END IF;
END IF;
END PROCESS p_sample;
p_cnt: PROCESS(r_sample, r_prev, r_cnt)
VARIABLE v_delta: signed(1 DOWNTO 0);
BEGIN
v_delta := signed(r_sample) - signed(r_prev);
n_cnt <= std_logic_vector(signed(r_cnt) + v_delta);
END PROCESS p_cnt;
p_sync: PROCESS(rst, clk)
