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b5b070d
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master
mips_sys
system
system.vhd
implented basic system with core, instr memory, data memory
Stefan Schuermans
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b5b070d
at 2012-02-06 21:28:00
system.vhd
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LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY e_system IS PORT ( rst: IN std_logic; clk: IN std_logic; i_prg_addr: IN std_logic_vector(31 DOWNTO 0); i_prg_data: IN std_logic_vector(31 DOWNTO 0); i_prg_en: IN std_logic; o_dummy: OUT std_logic_vector(31 DOWNTO 0) ); END ENTITY e_system; ARCHITECTURE a_system OF e_system IS SIGNAL s_instr_addr: std_logic_vector(31 DOWNTO 0); SIGNAL s_instr_data: std_logic_vector(31 DOWNTO 0); SIGNAL s_data_addr: std_logic_vector(31 DOWNTO 0); SIGNAL s_data_rd_data: std_logic_vector(31 DOWNTO 0); SIGNAL s_data_wr_data: std_logic_vector(31 DOWNTO 0); SIGNAL s_data_wr_en: std_logic_vector( 3 DOWNTO 0); COMPONENT e_mips_core IS PORT ( rst: IN std_logic; clk: IN std_logic; i_stall: IN std_logic; o_instr_addr: OUT std_logic_vector(31 DOWNTO 0); i_instr_data: IN std_logic_vector(31 DOWNTO 0); o_data_addr: OUT std_logic_vector(31 DOWNTO 0); i_data_rd_data: IN std_logic_vector(31 DOWNTO 0); o_data_wr_data: OUT std_logic_vector(31 DOWNTO 0); o_data_wr_en: OUT std_logic_vector( 3 DOWNTO 0) ); END COMPONENT e_mips_core; COMPONENT e_ram IS GENERIC ( addr_width: natural; data_width: natural ); PORT ( clk: IN std_logic; i_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0); o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0); i_wr_data: IN std_logic_vector(data_width - 1 DOWNTO 0); i_wr_en: IN std_logic ); END COMPONENT e_ram; COMPONENT e_dpram IS GENERIC ( addr_width: natural; data_width: natural ); PORT ( clk: IN std_logic; i_rd_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0); o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0); i_wr_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0); i_wr_data: IN std_logic_vector(data_width - 1 DOWNTO 0); i_wr_en: IN std_logic ); END COMPONENT e_dpram; BEGIN core: e_mips_core PORT MAP ( rst => rst, clk => clk, i_stall => '0', o_instr_addr => s_instr_addr, i_instr_data => s_instr_data, o_data_addr => s_data_addr, i_data_rd_data => s_data_rd_data, o_data_wr_data => s_data_wr_data, o_data_wr_en => s_data_wr_en ); instr: e_dpram GENERIC MAP ( addr_width => 10, data_width => 32 ) PORT MAP ( clk => clk, i_rd_addr => s_instr_addr(11 DOWNTO 2), o_rd_data => s_instr_data, i_wr_addr => i_prg_addr(11 DOWNTO 2), i_wr_data => i_prg_data, i_wr_en => i_prg_en ); data: FOR i IN 0 TO 3 GENERATE databank: e_ram GENERIC MAP ( addr_width => 10, data_width => 8 ) PORT MAP ( clk => clk, i_addr => s_data_addr(11 DOWNTO 2), o_rd_data => s_data_rd_data(i*8+7 DOWNTO i*8), i_wr_data => s_data_wr_data(i*8+7 DOWNTO i*8), i_wr_en => s_data_wr_en(i) ); END GENERATE data; o_dummy <= s_data_wr_data; END ARCHITECTURE a_system;
