LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.io_lcd_pins.all;
USE work.io_switches_pins.all;
ENTITY e_system IS
PORT (
clk: IN std_logic;
pin_o_leds: OUT std_logic_vector(7 DOWNTO 0);
pin_o_lcd: OUT t_io_lcd_pins;
pin_i_switches: IN t_io_switches_pins;
pin_i_uart_rx: IN std_logic;
pin_o_uart_tx: OUT std_logic;
pin_o_eth_nrst: OUT std_logic;
pin_i_eth_rx_clk: IN std_logic;
pin_i_eth_rxd: IN std_logic_vector(4 DOWNTO 0);
pin_i_eth_rx_dv: IN std_logic;
pin_i_eth_crs: IN std_logic;
pin_i_eth_col: IN std_logic;
pin_i_eth_tx_clk: IN std_logic;
pin_o_eth_txd: OUT std_logic_vector(3 DOWNTO 0);
pin_o_eth_tx_en: OUT std_logic
);
END ENTITY e_system;
ARCHITECTURE a_system OF e_system IS
CONSTANT c_instr_addr_width: natural := 14;
CONSTANT c_data_addr_width: natural := 13;
SIGNAL rst: std_logic := '0';
SIGNAL s_instr_addr: std_logic_vector(31 DOWNTO 0);
SIGNAL s_instr_data: std_logic_vector(31 DOWNTO 0);
SIGNAL s_core_req: std_logic;
SIGNAL s_core_grant: std_logic;
SIGNAL s_core_addr: std_logic_vector(31 DOWNTO 0);
SIGNAL s_core_rd_data: std_logic_vector(31 DOWNTO 0);
SIGNAL s_core_rd_en: std_logic_vector( 3 DOWNTO 0);
SIGNAL s_core_wr_data: std_logic_vector(31 DOWNTO 0);
SIGNAL s_core_wr_en: std_logic_vector( 3 DOWNTO 0);
SIGNAL s_ethbm_req: std_logic;
SIGNAL s_ethbm_grant: std_logic;
SIGNAL s_ethbm_addr: std_logic_vector(31 DOWNTO 0);
SIGNAL s_ethbm_rd_data: std_logic_vector(31 DOWNTO 0);
SIGNAL s_ethbm_rd_en: std_logic_vector( 3 DOWNTO 0);
SIGNAL s_ethbm_wr_data: std_logic_vector(31 DOWNTO 0);
SIGNAL s_ethbm_wr_en: std_logic_vector( 3 DOWNTO 0);
