mips_sys

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.mips_types.all;
ENTITY e_mips_mul IS
    PORT (
        rst:      IN  std_logic;
        clk:      IN  std_logic;
        i_a:      IN  std_logic_vector(31 DOWNTO 0);
        i_b:      IN  std_logic_vector(31 DOWNTO 0);
        i_signed: IN  std_logic;
        i_start:  IN  std_logic;
        o_busy:   OUT std_logic;
        o_res:    OUT std_logic_vector(63 DOWNTO 0)
    );
END ENTITY e_mips_mul;
ARCHITECTURE a_mips_mul OF e_mips_mul IS
    TYPE t_state IS (idle, state_1, state_2, state_3, state_4, post);
    SIGNAL n_state: t_state;
    SIGNAL r_state: t_state := idle;
    SIGNAL n_a:   unsigned(31 DOWNTO 0);
    SIGNAL n_b:   unsigned(31 DOWNTO 0);
    SIGNAL n_neg: boolean;
    SIGNAL n_res: unsigned(63 DOWNTO 0);
    SIGNAL r_a:   unsigned(31 DOWNTO 0) := (OTHERS => '0');
    SIGNAL r_b:   unsigned(31 DOWNTO 0) := (OTHERS => '0');
    SIGNAL r_neg: boolean               := false;
    SIGNAL r_res: unsigned(63 DOWNTO 0) := (OTHERS => '0');
BEGIN
    p_mul: PROCESS(r_state, r_a, r_b, r_neg, r_res,
                   i_a, i_b, i_signed, i_start)
        VARIABLE v_a:   unsigned(15 DOWNTO 0);
        VARIABLE v_b:   unsigned(15 DOWNTO 0);
        VARIABLE v_res: unsigned(31 DOWNTO 0);
        VARIABLE v_add: unsigned(63 DOWNTO 0);
        VARIABLE v_sum: unsigned(63 DOWNTO 0);
    BEGIN
        o_busy  <= '0';
        n_state <= idle;
        n_a     <= r_a;
        n_b     <= r_b;
        n_neg   <= r_neg;
        n_res   <= r_res;
        v_a     := (OTHERS => '0');
        v_b     := (OTHERS => '0');
 
 
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