LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.mips_types.all;
ENTITY e_mips_div IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
i_num: IN std_logic_vector(31 DOWNTO 0);
i_denom: IN std_logic_vector(31 DOWNTO 0);
i_signed: IN std_logic;
i_start: IN std_logic;
o_busy: OUT std_logic;
o_res: OUT std_logic_vector(31 DOWNTO 0);
o_rem: OUT std_logic_vector(31 DOWNTO 0)
);
END ENTITY e_mips_div;
ARCHITECTURE a_mips_div OF e_mips_div IS
SUBTYPE t_state IS natural RANGE 0 TO 33;
SIGNAL n_state: t_state;
SIGNAL r_state: t_state := 0;
SIGNAL n_num: signed(63 DOWNTO 0);
SIGNAL n_denom: signed(63 DOWNTO 0);
SIGNAL n_neg: boolean;
SIGNAL n_res: signed(31 DOWNTO 0);
SIGNAL r_num: signed(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL r_denom: signed(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL r_neg: boolean := false;
SIGNAL r_res: signed(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_rem: signed(31 DOWNTO 0) := (OTHERS => '0');
BEGIN
p_div: PROCESS(r_state, r_num, r_denom, r_neg, r_res,
i_num, i_denom, i_signed, i_start)
VARIABLE v_num: signed(31 DOWNTO 0);
VARIABLE v_denom: signed(31 DOWNTO 0);
VARIABLE v_diff: signed(63 DOWNTO 0);
BEGIN
o_busy <= '0';
n_state <= r_state;
n_num <= r_num;
n_denom <= r_denom;
n_neg <= r_neg;
n_res <= r_res;
s_rem <= (OTHERS => '0');
CASE r_state IS
