mips_sys

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.mips_types.all;
ENTITY e_mips_core IS
    PORT (
        rst:            IN  std_logic;
        clk:            IN  std_logic;
        o_instr_addr:   OUT std_logic_vector(31 DOWNTO 0);
        i_instr_data:   IN  std_logic_vector(31 DOWNTO 0);
        o_data_req:     OUT std_logic;
        i_data_grant:   IN  std_logic;
        o_data_addr:    OUT std_logic_vector(31 DOWNTO 0);
        i_data_rd_data: IN  std_logic_vector(31 DOWNTO 0);
        o_data_rd_en:   OUT std_logic_vector( 3 DOWNTO 0);
        o_data_wr_data: OUT std_logic_vector(31 DOWNTO 0);
        o_data_wr_en:   OUT std_logic_vector( 3 DOWNTO 0)
    );
END ENTITY e_mips_core;
ARCHITECTURE a_mips_core OF e_mips_core IS
    SIGNAL s_stall:         std_logic;
    SIGNAL r_stall_reset:   std_logic := '1';
    SIGNAL s_stall_data_rd: std_logic;
    SIGNAL s_stall_data_wr: std_logic;
    SIGNAL r_pc:         std_logic_vector(31 DOWNTO 0) := X"FFFFFFFC";
    SIGNAL n_pc:         std_logic_vector(31 DOWNTO 0);
    SIGNAL r_instr_data: std_logic_vector(31 DOWNTO 0) := X"00000000";
    SIGNAL s_instr:      std_logic_vector(31 DOWNTO 0);
    SIGNAL n_reg_s:  std_logic_vector( 4 DOWNTO 0);
    SIGNAL n_reg_t:  std_logic_vector( 4 DOWNTO 0);
    SIGNAL n_reg_d:  std_logic_vector( 4 DOWNTO 0);
    SIGNAL n_imm_a:  std_logic_vector( 4 DOWNTO 0);
    SIGNAL n_imm_16: std_logic_vector(15 DOWNTO 0);
    SIGNAL n_imm_26: std_logic_vector(25 DOWNTO 0);
    SIGNAL n_op:     t_op;
    SIGNAL n_link:   t_link;
    SIGNAL n_cmp:    t_cmp;
    SIGNAL n_alu:    t_alu;
    SIGNAL n_imm:    t_imm;
    SIGNAL n_ldst:   t_ldst;
    SIGNAL r_reg_s:  std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0');
    SIGNAL r_reg_t:  std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0');
    SIGNAL r_reg_d:  std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0');
    SIGNAL r_imm_a:  std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0');
    SIGNAL r_imm_16: std_logic_vector(15 DOWNTO 0) := (OTHERS => '0');
 
 
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