LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.mips_types.all;
ENTITY e_mips_alu IS
PORT (
i_alu: IN t_alu;
i_op1: IN std_logic_vector(31 DOWNTO 0);
i_op2: IN std_logic_vector(31 DOWNTO 0);
o_res: OUT std_logic_vector(31 DOWNTO 0)
);
END ENTITY e_mips_alu;
ARCHITECTURE a_mips_alu OF e_mips_alu IS
SIGNAL s_shift_arith: std_logic;
SIGNAL s_shift_left: std_logic;
SIGNAL s_shift_out: std_logic_vector(31 DOWNTO 0);
COMPONENT e_mips_shifter IS
PORT (
i_arith: IN std_logic;
i_left: IN std_logic;
i_val: IN std_logic_vector(31 DOWNTO 0);
i_num: IN std_logic_vector(31 DOWNTO 0);
o_val: OUT std_logic_vector(31 DOWNTO 0)
);
END COMPONENT e_mips_shifter;
BEGIN
shifter: e_mips_shifter
PORT MAP (
i_arith => s_shift_arith,
i_left => s_shift_left,
i_val => i_op2,
i_num => i_op1,
o_val => s_shift_out
);
p_alu: PROCESS(i_alu, i_op1, i_op2, s_shift_out)
VARIABLE v_op1_s: signed(31 DOWNTO 0);
VARIABLE v_op2_s: signed(31 DOWNTO 0);
VARIABLE v_op1_u: unsigned(31 DOWNTO 0);
VARIABLE v_op2_u: unsigned(31 DOWNTO 0);
BEGIN
v_op1_s := signed(i_op1);
v_op2_s := signed(i_op2);
v_op1_u := unsigned(i_op1);
v_op2_u := unsigned(i_op2);
