mips_sys

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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY e_io_uart IS
    PORT (
        rst:       IN  std_logic;
        clk:       IN  std_logic;
        i_addr:    IN  std_logic_vector( 1 DOWNTO 0);
        o_rd_data: OUT std_logic_vector(31 DOWNTO 0);
        i_rd_en:   IN  std_logic_vector( 3 DOWNTO 0);
        i_wr_data: IN  std_logic_vector(31 DOWNTO 0);
        i_wr_en:   IN  std_logic_vector( 3 DOWNTO 0);
        pin_i_rx:  IN  std_logic;
        pin_o_tx:  OUT std_logic
    );
END ENTITY e_io_uart;
ARCHITECTURE a_io_uart OF e_io_uart IS
    TYPE t_state IS (inactive, start, data, stop);
    SIGNAL n_cfg_scale: std_logic_vector(15 DOWNTO 0);
    SIGNAL r_cfg_scale: std_logic_vector(15 DOWNTO 0) := X"0001";
    SIGNAL n_cfg_bits:  std_logic_vector( 3 DOWNTO 0);
    SIGNAL r_cfg_bits:  std_logic_vector( 3 DOWNTO 0) := X"1";
    SIGNAL n_cfg_stop:  std_logic_vector( 1 DOWNTO 0);
    SIGNAL r_cfg_stop:  std_logic_vector( 1 DOWNTO 0) := "01";
    SIGNAL s_rx_wr_rdy:  std_logic;
    SIGNAL s_rx_wr_data: std_logic_vector(15 DOWNTO 0);
    SIGNAL s_rx_wr_en:   std_logic;
    SIGNAL s_rx_rd_rdy:  std_logic;
    SIGNAL s_rx_rd_data: std_logic_vector(15 DOWNTO 0);
    SIGNAL s_rx_rd_en:   std_logic;
    SIGNAL n_rx_scale:   natural RANGE 2**16 - 1 DOWNTO 0;
    SIGNAL r_rx_scale:   natural RANGE 2**16 - 1 DOWNTO 0 := 1;
    SIGNAL n_rx_bits:    natural RANGE 15        DOWNTO 0;
    SIGNAL r_rx_bits:    natural RANGE 15        DOWNTO 0 := 1;
    SIGNAL n_rx_stop:    natural RANGE 3         DOWNTO 0;
    SIGNAL r_rx_stop:    natural RANGE 3         DOWNTO 0 := 1;
    SIGNAL n_rx_state:   t_state;
    SIGNAL r_rx_state:   t_state                          := inactive;
    SIGNAL n_rx_cnt:     natural RANGE 2**16 - 1 DOWNTO 0;
    SIGNAL r_rx_cnt:     natural RANGE 2**16 - 1 DOWNTO 0 := 0;
    SIGNAL n_rx_sample:  natural RANGE 6         DOWNTO 0;
    SIGNAL r_rx_sample:  natural RANGE 6         DOWNTO 0 := 0;
    SIGNAL n_rx_bit:     natural RANGE 15        DOWNTO 0;
    SIGNAL r_rx_bit:     natural RANGE 15        DOWNTO 0 := 0;
    SIGNAL n_rx_samples: std_logic_vector( 1 DOWNTO 0);
 
 
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