LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.io_switches_pins.all;
ENTITY e_io_switches IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
i_addr: IN std_logic_vector( 0 DOWNTO 0);
o_rd_data: OUT std_logic_vector(31 DOWNTO 0);
pin_i_switches: IN t_io_switches_pins
);
END ENTITY e_io_switches;
ARCHITECTURE a_io_switches OF e_io_switches IS
CONSTANT c_scale: natural := 50000;
CONSTANT c_states: natural := 5;
SUBTYPE t_state IS std_logic_vector(31 DOWNTO 0);
TYPE t_states IS ARRAY(0 TO c_states - 1) OF t_state;
CONSTANT c_state_def: t_state := io_switches_to_slv(
c_io_switches_pins_default);
CONSTANT c_states_def: t_states := (OTHERS => c_state_def);
SIGNAL n_scale: natural RANGE 0 TO c_scale - 1;
SIGNAL r_scale: natural RANGE 0 TO c_scale - 1 := 0;
SIGNAL n_states: t_states;
SIGNAL r_states: t_states := c_states_def;
SIGNAL n_debounced: t_state;
SIGNAL r_debounced: t_state := c_state_def;
SIGNAL n_rot_val: std_logic_vector( 1 DOWNTO 0);
SIGNAL r_rot_val: std_logic_vector( 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL r_rot_prev: std_logic_vector( 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL n_rot_cnt: std_logic_vector(31 DOWNTO 0);
SIGNAL r_rot_cnt: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
BEGIN
p_scale: PROCESS(r_scale)
BEGIN
IF r_scale >= c_scale - 1 THEN
n_scale <= 0;
ELSE
n_scale <= r_scale + 1;
END IF;
