LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY e_io_eth_txframe IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
o_if_data: OUT std_logic_vector(7 DOWNTO 0);
o_if_data_en: OUT std_logic;
i_if_data_ack: IN std_logic;
i_frame_en: IN std_logic;
i_frame_data: IN std_logic_vector(31 DOWNTO 0);
i_frame_data_en: IN std_logic;
o_frame_data_ack: OUT std_logic;
o_frame_done: OUT std_logic
);
END ENTITY e_io_eth_txframe;
ARCHITECTURE a_io_eth_txframe OF e_io_eth_txframe IS
TYPE t_state IS (st_idle, st_sync, st_start, st_data,
st_pad, st_crc, st_gap);
SUBTYPE t_data_cnt IS natural RANGE 0 TO 3;
SUBTYPE t_byte_cnt IS natural RANGE 0 TO 255;
SIGNAL r_state: t_state := st_idle;
SIGNAL n_state: t_state;
SIGNAL r_data_cnt: t_data_cnt := 0;
SIGNAL n_data_cnt: t_data_cnt;
SIGNAL r_data: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL n_data: std_logic_vector(31 DOWNTO 0);
SIGNAL r_byte_cnt: t_byte_cnt := 0;
SIGNAL n_byte_cnt: t_byte_cnt;
SIGNAL r_crc_start: std_logic := '0';
SIGNAL n_crc_start: std_logic;
SIGNAL s_crc_en: std_logic;
SIGNAL s_crc_start: std_logic;
SIGNAL s_crc_data: std_logic_vector( 7 DOWNTO 0);
SIGNAL s_crc_crc: std_logic_vector(31 DOWNTO 0);
COMPONENT e_block_crc32 IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
i_en: IN std_logic;
i_start: IN std_logic;
i_data: IN std_logic_vector( 7 DOWNTO 0);
o_crc: OUT std_logic_vector(31 DOWNTO 0)
