LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY e_io_eth_rxframe IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
i_data: IN std_logic_vector( 7 DOWNTO 0);
i_data_en: IN std_logic;
i_done: IN std_logic;
i_err: IN std_logic;
i_mac: IN std_logic_vector(47 DOWNTO 0);
o_data: OUT std_logic_vector(31 DOWNTO 0);
o_data_en: OUT std_logic;
o_done: OUT std_logic;
o_err: OUT std_logic
);
END ENTITY e_io_eth_rxframe;
ARCHITECTURE a_io_eth_rxframe OF e_io_eth_rxframe IS
TYPE t_state IS (st_idle, st_sync, st_mac, st_mac_uni, st_mac_brd, st_data);
SUBTYPE t_mac_cnt IS natural RANGE 0 TO 5;
SUBTYPE t_data_cnt IS natural RANGE 0 TO 3;
SIGNAL r_state: t_state := st_idle;
SIGNAL n_state: t_state;
SIGNAL r_mac_cnt: t_mac_cnt := 0;
SIGNAL n_mac_cnt: t_mac_cnt;
SIGNAL r_data_cnt: t_data_cnt := 0;
SIGNAL n_data_cnt: t_data_cnt;
SIGNAL r_out_data: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL n_out_data: std_logic_vector(31 DOWNTO 0);
SIGNAL r_out_data_en: std_logic := '0';
SIGNAL n_out_data_en: std_logic;
SIGNAL r_out_done: std_logic := '0';
SIGNAL n_out_done: std_logic;
SIGNAL r_out_err: std_logic := '0';
SIGNAL n_out_err: std_logic;
SIGNAL s_crc_en: std_logic;
SIGNAL s_crc_start: std_logic;
SIGNAL s_crc_data: std_logic_vector( 7 DOWNTO 0);
SIGNAL s_crc_crc: std_logic_vector(31 DOWNTO 0);
COMPONENT e_block_crc32 IS
PORT (
rst: IN std_logic;
