mips_sys

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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY e_io_eth IS
    PORT (
        rst:          IN  std_logic;
        clk:          IN  std_logic;
        i_addr:       IN  std_logic_vector( 3 DOWNTO 0);
        o_rd_data:    OUT std_logic_vector(31 DOWNTO 0);
        i_rd_en:      IN  std_logic_vector( 3 DOWNTO 0);
        i_wr_data:    IN  std_logic_vector(31 DOWNTO 0);
        i_wr_en:      IN  std_logic_vector( 3 DOWNTO 0);
        o_bm_req:     OUT std_logic;
        i_bm_grant:   IN  std_logic;
        o_bm_addr:    OUT std_logic_vector(31 DOWNTO 0);
        i_bm_rd_data: IN  std_logic_vector(31 DOWNTO 0);
        o_bm_rd_en:   OUT std_logic_vector( 3 DOWNTO 0);
        o_bm_wr_data: OUT std_logic_vector(31 DOWNTO 0);
        o_bm_wr_en:   OUT std_logic_vector( 3 DOWNTO 0);
        pin_o_nrst:   OUT std_logic;
        pin_i_rx_clk: IN  std_logic;
        pin_i_rxd:    IN  std_logic_vector(4 DOWNTO 0);
        pin_i_rx_dv:  IN  std_logic;
        pin_i_crs:    IN  std_logic;
        pin_i_col:    IN  std_logic;
        pin_i_tx_clk: IN  std_logic;
        pin_o_txd:    OUT std_logic_vector(3 DOWNTO 0);
        pin_o_tx_en:  OUT std_logic
    );
END ENTITY e_io_eth;
ARCHITECTURE a_io_eth OF e_io_eth IS
    SIGNAL s_rxif_data:    std_logic_vector(7 DOWNTO 0);
    SIGNAL s_rxif_data_en: std_logic;
    SIGNAL s_rxif_done:    std_logic;
    SIGNAL s_rxif_err:     std_logic;
    SIGNAL s_rxframe_data:    std_logic_vector(31 DOWNTO 0);
    SIGNAL s_rxframe_data_en: std_logic;
    SIGNAL s_rxframe_done:    std_logic;
    SIGNAL s_rxframe_err:     std_logic;
    SIGNAL s_rx_new: std_logic;
    SIGNAL s_txif_data:     std_logic_vector(7 DOWNTO 0);
    SIGNAL s_txif_data_en:  std_logic;
    SIGNAL s_txif_data_ack: std_logic;
    SIGNAL s_txframe_en:   std_logic;
 
 
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