LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.mips_types.all;
ENTITY e_mips_core IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
o_res: OUT std_logic_vector(31 DOWNTO 0)
);
END ENTITY e_mips_core;
ARCHITECTURE a_mips_core OF e_mips_core IS
SIGNAL r_instr: std_logic_vector(31 DOWNTO 0);
SIGNAL s_src_s: std_logic_vector( 4 DOWNTO 0);
SIGNAL s_src_t: std_logic_vector( 4 DOWNTO 0);
SIGNAL s_dest: std_logic_vector( 4 DOWNTO 0);
SIGNAL s_imm_a: std_logic_vector( 4 DOWNTO 0);
SIGNAL s_imm_16: std_logic_vector(15 DOWNTO 0);
SIGNAL s_imm_26: std_logic_vector(25 DOWNTO 0);
SIGNAL s_op: t_op;
SIGNAL s_link: t_link;
SIGNAL s_cmp: t_cmp;
SIGNAL s_alu: t_alu;
SIGNAL s_imm: t_imm;
SIGNAL s_op1: std_logic_vector(31 DOWNTO 0);
SIGNAL s_op2: std_logic_vector(31 DOWNTO 0);
SIGNAL s_res: std_logic_vector(31 DOWNTO 0);
COMPONENT e_mips_decoder IS
PORT (
i_instr: IN std_logic_vector(31 DOWNTO 0);
o_src_s: OUT std_logic_vector( 4 DOWNTO 0);
o_src_t: OUT std_logic_vector( 4 DOWNTO 0);
o_dest: OUT std_logic_vector( 4 DOWNTO 0);
o_imm_a: OUT std_logic_vector( 4 DOWNTO 0);
o_imm_16: OUT std_logic_vector(15 DOWNTO 0);
o_imm_26: OUT std_logic_vector(25 DOWNTO 0);
o_op: OUT t_op;
o_link: OUT t_link;
o_cmp: OUT t_cmp;
o_alu: OUT t_alu;
o_imm: OUT t_imm
);
END COMPONENT e_mips_decoder;
COMPONENT e_mips_regs IS
