increased code and data address range to 8KB
Stefan Schuermans commited on 2012-02-20 15:55:19
Showing 3 changed files, with 27 additions and 15 deletions.
- fw/boot.s 8576c9a..ad5bf19
- fw/lnk.cmd 8049f84..4a8485a
- system/system.vhd 6e50e7e..0c49c5f
| ... | ... |
@@ -1,8 +1,17 @@ |
| 1 | 1 |
SECTIONS |
| 2 | 2 |
{
|
| 3 | 3 |
. = 0x00000000; |
| 4 |
- .rom : { *(.text) }
|
|
| 5 |
- . = 0x00001000; |
|
| 6 |
- .ram : { *(.rodata) *(.data) *(.bss) *(*COM*) }
|
|
| 4 |
+ .rom : {
|
|
| 5 |
+ *(.text) |
|
| 6 |
+ . = 0x00002000; |
|
| 7 |
+ } |
|
| 8 |
+ . = 0x00010000; |
|
| 9 |
+ .ram : {
|
|
| 10 |
+ *(.rodata) |
|
| 11 |
+ *(.data) |
|
| 12 |
+ *(.bss) |
|
| 13 |
+ *(*COM*) |
|
| 14 |
+ . = 0x00002000; |
|
| 15 |
+ } |
|
| 7 | 16 |
} |
| 8 | 17 |
|
| ... | ... |
@@ -17,6 +17,9 @@ END ENTITY e_system; |
| 17 | 17 |
|
| 18 | 18 |
ARCHITECTURE a_system OF e_system IS |
| 19 | 19 |
|
| 20 |
+ CONSTANT c_instr_addr_width: natural := 13; |
|
| 21 |
+ CONSTANT c_data_addr_width: natural := 13; |
|
| 22 |
+ |
|
| 20 | 23 |
SIGNAL rst: std_logic := '0'; |
| 21 | 24 |
|
| 22 | 25 |
SIGNAL s_instr_addr: std_logic_vector(31 DOWNTO 0); |
| ... | ... |
@@ -194,11 +197,11 @@ BEGIN |
| 194 | 197 |
|
| 195 | 198 |
instr: e_rom |
| 196 | 199 |
GENERIC MAP ( |
| 197 |
- addr_width => 10 |
|
| 200 |
+ addr_width => c_instr_addr_width - 2 |
|
| 198 | 201 |
) |
| 199 | 202 |
PORT MAP ( |
| 200 | 203 |
clk => clk, |
| 201 |
- i_addr => s_instr_addr(11 DOWNTO 2), |
|
| 204 |
+ i_addr => s_instr_addr(c_instr_addr_width - 1 DOWNTO 2), |
|
| 202 | 205 |
o_data => s_instr_data |
| 203 | 206 |
); |
| 204 | 207 |
|
| ... | ... |
@@ -261,11 +264,11 @@ BEGIN |
| 261 | 264 |
|
| 262 | 265 |
data_0: e_ram_0 |
| 263 | 266 |
GENERIC MAP ( |
| 264 |
- addr_width => 10 |
|
| 267 |
+ addr_width => c_data_addr_width - 2 |
|
| 265 | 268 |
) |
| 266 | 269 |
PORT MAP ( |
| 267 | 270 |
clk => clk, |
| 268 |
- i_addr => s_data_addr(11 DOWNTO 2), |
|
| 271 |
+ i_addr => s_data_addr(c_data_addr_width - 1 DOWNTO 2), |
|
| 269 | 272 |
o_rd_data => s_data_rd_data(7 DOWNTO 0), |
| 270 | 273 |
i_wr_data => s_data_wr_data(7 DOWNTO 0), |
| 271 | 274 |
i_wr_en => s_data_wr_en(0) |
| ... | ... |
@@ -273,11 +276,11 @@ BEGIN |
| 273 | 276 |
|
| 274 | 277 |
data_1: e_ram_1 |
| 275 | 278 |
GENERIC MAP ( |
| 276 |
- addr_width => 10 |
|
| 279 |
+ addr_width => c_data_addr_width - 2 |
|
| 277 | 280 |
) |
| 278 | 281 |
PORT MAP ( |
| 279 | 282 |
clk => clk, |
| 280 |
- i_addr => s_data_addr(11 DOWNTO 2), |
|
| 283 |
+ i_addr => s_data_addr(c_data_addr_width - 1 DOWNTO 2), |
|
| 281 | 284 |
o_rd_data => s_data_rd_data(15 DOWNTO 8), |
| 282 | 285 |
i_wr_data => s_data_wr_data(15 DOWNTO 8), |
| 283 | 286 |
i_wr_en => s_data_wr_en(1) |
| ... | ... |
@@ -285,11 +288,11 @@ BEGIN |
| 285 | 288 |
|
| 286 | 289 |
data_2: e_ram_2 |
| 287 | 290 |
GENERIC MAP ( |
| 288 |
- addr_width => 10 |
|
| 291 |
+ addr_width => c_data_addr_width - 2 |
|
| 289 | 292 |
) |
| 290 | 293 |
PORT MAP ( |
| 291 | 294 |
clk => clk, |
| 292 |
- i_addr => s_data_addr(11 DOWNTO 2), |
|
| 295 |
+ i_addr => s_data_addr(c_data_addr_width - 1 DOWNTO 2), |
|
| 293 | 296 |
o_rd_data => s_data_rd_data(23 DOWNTO 16), |
| 294 | 297 |
i_wr_data => s_data_wr_data(23 DOWNTO 16), |
| 295 | 298 |
i_wr_en => s_data_wr_en(2) |
| ... | ... |
@@ -297,11 +300,11 @@ BEGIN |
| 297 | 300 |
|
| 298 | 301 |
data_3: e_ram_3 |
| 299 | 302 |
GENERIC MAP ( |
| 300 |
- addr_width => 10 |
|
| 303 |
+ addr_width => c_data_addr_width - 2 |
|
| 301 | 304 |
) |
| 302 | 305 |
PORT MAP ( |
| 303 | 306 |
clk => clk, |
| 304 |
- i_addr => s_data_addr(11 DOWNTO 2), |
|
| 307 |
+ i_addr => s_data_addr(c_data_addr_width - 1 DOWNTO 2), |
|
| 305 | 308 |
o_rd_data => s_data_rd_data(31 DOWNTO 24), |
| 306 | 309 |
i_wr_data => s_data_wr_data(31 DOWNTO 24), |
| 307 | 310 |
i_wr_en => s_data_wr_en(3) |
| 308 | 311 |